5-V-only one-transistor 256K EEPROM with page-mode erase

Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

研究成果: Article査読

6 被引用数 (Scopus)

抄録

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is five per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5-μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7 × 8 μm2 and the chip size is 5.55 × 7.05 mm2. The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC.

本文言語English
ページ(範囲)911-915
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
24
4
DOI
出版ステータスPublished - 1989 8
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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