5-V-only one-transistor 256K EEPROM with page-mode erase

Takeshi Nakayama; Yoshikazu Miyawaki; Kazuo Kobayashi; Yasushi Terada; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara

doi:10.1109/4.34070

5-V-only one-transistor 256K EEPROM with page-mode erase

Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

研究成果: Article

6 引用（Scopus）

抜粋

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is five per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5-μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7 × 8 μm² and the chip size is 5.55 × 7.05 mm². The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC.

元の言語	English
ページ（範囲）	911-915
ページ数	5
ジャーナル	IEEE Journal of Solid-State Circuits
巻	24
発行部数	4
DOI	https://doi.org/10.1109/4.34070
出版物ステータス	Published - 1989 8
外部発表	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

文献にアクセス

10.1109/4.34070

フィンガープリント 5-V-only one-transistor 256K EEPROM with page-mode erase' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

これを引用

Nakayama, T., Miyawaki, Y., Kobayashi, K., Terada, Y., Arima, H., Matsukawa, T., & Yoshihara, T. (1989). 5-V-only one-transistor 256K EEPROM with page-mode erase. IEEE Journal of Solid-State Circuits, 24(4), 911-915. https://doi.org/10.1109/4.34070

@article{07c726a45b0049d984318ad15ec107bf,

title = "5-V-only one-transistor 256K EEPROM with page-mode erase",

abstract = "Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is five per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5-μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7 × 8 μm2 and the chip size is 5.55 × 7.05 mm2. The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC.",

author = "Takeshi Nakayama and Yoshikazu Miyawaki and Kazuo Kobayashi and Yasushi Terada and Hideaki Arima and Takayuki Matsukawa and Tsutomu Yoshihara",

year = "1989",

month = aug,

doi = "10.1109/4.34070",

language = "English",

volume = "24",

pages = "911--915",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - 5-V-only one-transistor 256K EEPROM with page-mode erase

AU - Nakayama, Takeshi

AU - Miyawaki, Yoshikazu

AU - Kobayashi, Kazuo

AU - Terada, Yasushi

AU - Arima, Hideaki

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

PY - 1989/8

Y1 - 1989/8

N2 - Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is five per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5-μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7 × 8 μm2 and the chip size is 5.55 × 7.05 mm2. The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC.

AB - Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is five per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5-μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7 × 8 μm2 and the chip size is 5.55 × 7.05 mm2. The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC.

UR - http://www.scopus.com/inward/record.url?scp=0024717906&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024717906&partnerID=8YFLogxK

U2 - 10.1109/4.34070

DO - 10.1109/4.34070

M3 - Article

AN - SCOPUS:0024717906

VL - 24

SP - 911

EP - 915

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -