50 ns video signal processor

Shin ichi Nakagawa*, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu ichi Kato, Atsushi Maeda, Yasutaka Horiba, Hideo Ohira, Yoshi aki Katoh, Mamoru Iwatsuki, Kin ya Tabuchi

*この研究の対応する著者

研究成果: Conference article査読

9 被引用数 (Scopus)

抄録

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0-μm double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.

本文言語English
ページ(範囲)168-169, 328
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
32
出版ステータスPublished - 1989 12 1
外部発表はい
イベントIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA
継続期間: 1989 2 151989 2 17

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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