TY - JOUR
T1 - 50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.
AU - Kaneko, Takao
AU - Yamauchi, Hironori
AU - Iwata, Atsushi
PY - 1986/12/1
Y1 - 1986/12/1
N2 - A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.
AB - A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.
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M3 - Conference article
AN - SCOPUS:0022908735
SP - 401
EP - 404
JO - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
JF - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
SN - 0736-7791
ER -