50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.

Takao Kaneko; Hironori Yamauchi; Atsushi Iwata

50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.

Takao Kaneko, Hironori Yamauchi, Atsushi Iwata

研究成果: Conference article › 査読

抄録

A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.

本文言語	English
ページ（範囲）	401-404
ページ数	4
ジャーナル	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
出版ステータス	Published - 1986 12 1
外部発表	はい

ASJC Scopus subject areas

Software
Signal Processing
Electrical and Electronic Engineering

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引用スタイル

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