A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.
|ホスト出版物のタイトル||1988 Symp VLSI Circuits Dig Tech Pap|
|出版物ステータス||Published - 1988|
|イベント||1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan|
継続期間: 1988 8 22 → 1988 8 24
|Other||1988 Symposium on VLSI Circuits - Digest of Technical Papers|
|期間||88/8/22 → 88/8/24|
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