5V only 1 Tr. 256K EEPROM with page mode erase

Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

研究成果: Conference contribution

4 引用 (Scopus)

抄録

A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.

元の言語English
ホスト出版物のタイトル1988 Symp VLSI Circuits Dig Tech Pap
編集者 Anon
ページ81-82
ページ数2
出版物ステータスPublished - 1988
外部発表Yes
イベント1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan
継続期間: 1988 8 221988 8 24

Other

Other1988 Symposium on VLSI Circuits - Digest of Technical Papers
Tokyo, Japan
期間88/8/2288/8/24

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Field emission
Transistors
Data storage equipment
Electric potential

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Nakayama, T., Miyawaki, Y., Kobayashi, K., Terada, Y., Arima, H., Matsukawa, T., & Yoshihara, T. (1988). 5V only 1 Tr. 256K EEPROM with page mode erase. : Anon (版), 1988 Symp VLSI Circuits Dig Tech Pap (pp. 81-82)

5V only 1 Tr. 256K EEPROM with page mode erase. / Nakayama, Takeshi; Miyawaki, Yoshikazu; Kobayashi, Kazuo; Terada, Yasushi; Arima, Hideaki; Matsukawa, Takayuki; Yoshihara, Tsutomu.

1988 Symp VLSI Circuits Dig Tech Pap. 版 / Anon. 1988. p. 81-82.

研究成果: Conference contribution

Nakayama, T, Miyawaki, Y, Kobayashi, K, Terada, Y, Arima, H, Matsukawa, T & Yoshihara, T 1988, 5V only 1 Tr. 256K EEPROM with page mode erase. : Anon (版), 1988 Symp VLSI Circuits Dig Tech Pap. pp. 81-82, 1988 Symposium on VLSI Circuits - Digest of Technical Papers, Tokyo, Japan, 88/8/22.
Nakayama T, Miyawaki Y, Kobayashi K, Terada Y, Arima H, Matsukawa T その他. 5V only 1 Tr. 256K EEPROM with page mode erase. : Anon, 編集者, 1988 Symp VLSI Circuits Dig Tech Pap. 1988. p. 81-82
Nakayama, Takeshi ; Miyawaki, Yoshikazu ; Kobayashi, Kazuo ; Terada, Yasushi ; Arima, Hideaki ; Matsukawa, Takayuki ; Yoshihara, Tsutomu. / 5V only 1 Tr. 256K EEPROM with page mode erase. 1988 Symp VLSI Circuits Dig Tech Pap. 編集者 / Anon. 1988. pp. 81-82
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N2 - A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.

AB - A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.

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