5V only 1 Tr. 256K EEPROM with page mode erase

Takeshi Nakayama*, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.

本文言語English
ホスト出版物のタイトル1988 Symp VLSI Circuits Dig Tech Pap
編集者 Anon
ページ81-82
ページ数2
出版ステータスPublished - 1988
外部発表はい
イベント1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan
継続期間: 1988 8 221988 8 24

Other

Other1988 Symposium on VLSI Circuits - Digest of Technical Papers
CityTokyo, Japan
Period88/8/2288/8/24

ASJC Scopus subject areas

  • 工学(全般)

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