60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

An auto selective boost (ASB) scheme for slow SRAM memory cells in random variations has been proposed. ASB shortens the cycle time and decreases the average BL amplitude, which reduces both dynamic and leakage energy dissipation. The cycle time of SRAM is reduced by 60% at 0.5V using the proposed ASB scheme. By combining the ASB with a BL amplitude limiter (BAL), the energy dissipation is reduced by 55%. A 32Kbit SRAM with the ASB and BAL schemes has been fabricated by 40nm CMOS technology.

元の言語English
ホスト出版物のタイトル2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
ページ317-320
ページ数4
DOI
出版物ステータスPublished - 2012 12 14
外部発表Yes
イベント38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France
継続期間: 2012 9 172012 9 21

出版物シリーズ

名前European Solid-State Circuits Conference
ISSN(印刷物)1930-8833

Other

Other38th European Solid State Circuits Conference, ESSCIRC 2012
France
Bordeaux
期間12/9/1712/9/21

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Yamamoto, Y., Kawasumi, A., Moriwaki, S., Suzuki, T., Miyano, S., & Shinohara, H. (2012). 60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. : 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012 (pp. 317-320). [6341318] (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2012.6341318