60 ns access 32 kByte 3-transistor flash for low power embedded applications

Tamio Ikehashi*, Junichiro Noda, Kenichi Imamiya, Masaaki Ichikawa, Akira Iwata, Takuya Futatsuyama

*この研究の対応する著者

研究成果: Paper査読

3 被引用数 (Scopus)

抄録

3-Transistor Flash (3-Tr) is a new flash memory suited for embedded application. The 32 kByte memory cell has the low power erase/program characteristic of NAND flash, and the size of the cell fabricated in a 0.4 um NAND flash technology is 4.36 μm2. This is about 1/8 of the EEPROM cells size with the same design rule. Two circuit technologies, a low power sensing scheme and a double stage boosting scheme, are proposed. The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during program mode.

本文言語English
ページ162-165
ページ数4
出版ステータスPublished - 2000 1 1
外部発表はい
イベント2000 Symposium on VLSI Circuits - Honolulu, HI, USA
継続期間: 2000 6 152000 6 17

Conference

Conference2000 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period00/6/1500/6/17

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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