61.5mW 2048-bit RSA cryptographic co-processor LSI based on N bit-wised modular multiplier

Toru Hisakado, Nobuyuki Kobayashi, Satoshi Goto, Takeshi Ikenaga, Kunihiko Higashi, Ichiro Kitao, Yukiyasu Tsunoo

研究成果: Conference contribution

3 引用 (Scopus)

抜粋

RSA, one of the public key cryptographies, is the most widely used for a wide variety of information systems. Especially, a compact, high-performance RSA LSI is highly desired for mobile applications, such as a smart card and a cellar phone. This paper describes a RSA Cryptography Co-processor LSI. It can process up to 2048-bit key data, which is requited to guarantee the high security level of RSA. Although a large computational complexity is required to process 2048-bit RSA, our proposed N bit-wise modular multiplier based on Montgomery multiplication algorithm enables to reduce 25% circuit amount compared with the conventional one. A chip capable of operating at 60 MHz was fabricated using 0.18 um TSMC CMOS technology. A total of 98.5 k gates (incl. SRAM and I/Q modules) have been integrated into a 2.2 × 2.2 mm chip. Evaluation result with IC test system shows that power dissipation is 61.5 mW when 20.48-bit RSA processing is operated at 40 MHz. This RSA LSI will make a significant contribution to the development of compact, high-performance secure information systems.

元の言語English
ホスト出版物のタイトル2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
ページ63-66
ページ数4
DOI
出版物ステータスPublished - 2007 10 1
イベント2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan, Province of China
継続期間: 2007 4 262007 4 28

出版物シリーズ

名前2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
Taiwan, Province of China
Hsinchu
期間07/4/2607/4/28

    フィンガープリント

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

これを引用

Hisakado, T., Kobayashi, N., Goto, S., Ikenaga, T., Higashi, K., Kitao, I., & Tsunoo, Y. (2007). 61.5mW 2048-bit RSA cryptographic co-processor LSI based on N bit-wised modular multiplier. : 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 63-66). [4027496] (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258124