We achieved 135 GHz fmax and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of Vth variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 2001 12月 1|
|イベント||IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States|
継続期間: 2001 12月 2 → 2001 12月 5
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