70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications

T. Matsumoto, S. Maeda, K. Ota, Y. Hirano, K. Eikyu, H. Sayama, T. Iwamatsu, K. Yamamoto*, T. Katoh, Y. Yamaguchi, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, M. Inuishi

*この研究の対応する著者

研究成果: Conference article査読

23 被引用数 (Scopus)

抄録

We achieved 135 GHz fmax and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of Vth variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

本文言語English
ページ(範囲)219-222
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 2001 12 1
外部発表はい
イベントIEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
継続期間: 2001 12 22001 12 5

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学
  • 材料化学

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