80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

H. Sayama^*, Y. Nishida, H. Oda, J. Tsuchimoto, H. Umeda, A. Teramoto, K. Eikyu, Y. Inoue, M. Inuishi

^*この研究の対応する著者

研究成果: Conference article › 査読