8.8-ns 54×54-bit multiplier using new redundant binary architecture

Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara

研究成果: Conference contribution

23 被引用数 (Scopus)

抄録

A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.

本文言語English
ホスト出版物のタイトルProceedings - IEEE International Conference on Computer Design
ホスト出版物のサブタイトルVLSI in Computers and Processors
編集者 Anon
出版社Publ by IEEE
ページ202-205
ページ数4
ISBN(印刷版)0818642300
出版ステータスPublished - 1993 12 1
外部発表はい
イベントProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA
継続期間: 1993 10 31993 10 6

出版物シリーズ

名前Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

OtherProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityCambridge, MA, USA
Period93/10/393/10/6

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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