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A 30-GHz band high-efficiency Class-J power amplifier IC in 120-nm SiGe HBT technology

Chen, C., Yang, X. & Yoshimasu, T., 2016 9 27, RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc., 7578122

研究成果: Conference contribution

2 引用 (Scopus)

A 30-GHz band low-insertion loss and high-isolation SPDT switch IC in 120-nm SiGe HBT

Chen, C., Tuo, F., Xu, X. & Yoshimasu, T., 2016 9 27, RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc., 7578134

研究成果: Conference contribution

1 引用 (Scopus)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

Morishita, F., Hayashi, I., Matsuoka, H., Takahashi, K., Shigeta, K., Gyohten, T., Niiro, M., Noda, H., Okamoto, M., Hachisuka, A., Amo, A., Shinkawata, H., Kasaoka, T., Dosaka, K., Arimoto, K., Fujishima, K., Anami, K. & Yoshihara, T., 2005 1, : : IEEE Journal of Solid-State Circuits. 40, 1, p. 204-210 7 p.

研究成果: Article

14 引用 (Scopus)

A 32Gbit/s 16QAM CMOS receiver in 300GHz band

Hara, S., Katayama, K., Takano, K., Dong, R., Watanabe, I., Sekine, N., Kasamatsu, A., Yoshida, T., Amakawa, S. & Fujishima, M., 2017 10 4, 2017 IEEE MTT-S International Microwave Symposium, IMS 2017. Institute of Electrical and Electronics Engineers Inc., p. 1703-1706 4 p. 8058969

研究成果: Conference contribution

30 引用 (Scopus)

A 32×32 two-dimensional photodetector array using a-Si pin photodiodes and poly-Si TFTs integrated on a transparent substrate

Okamura, M., Kimura, K., Shirai, S. & Yamauchi, N., 1992 1 1, 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992. Institute of Electrical and Electronics Engineers Inc., p. 685-688 4 p. 307452. (Technical Digest - International Electron Devices Meeting, IEDM; 巻数 1992-December).

研究成果: Conference contribution

1 引用 (Scopus)

A 333MHz random cycle DRAM using the floating body cell

Hatsuda, K., Fujita, K. & Ohsawa, T., 2005 12 1, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference. p. 256-259 4 p. 1568656. (Proceedings of the Custom Integrated Circuits Conference; 巻数 2005).

研究成果: Conference contribution

8 引用 (Scopus)

A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon

Wada, T., Hirose, T., Shinohara, H., Kawai, Y., Yuzuriha, K., Kohno, Y. & Kayano, S., 1987 10, : : IEEE Journal of Solid-State Circuits. 22, 5, p. 727-732 6 p.

研究成果: Article

12 引用 (Scopus)

A 35 ns 16K NMOS Static RAM

Anami, K., Yoshimoto, M., Shinohara, H., Hirata, Y., Harada, H. & Nakano, T., 1982 10, : : IEEE Journal of Solid-State Circuits. 17, 5, p. 815-820 6 p.

研究成果: Article

1 引用 (Scopus)

A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

Hong, Y., Liu, P., Zhang, H., You, Z., Zhou, D. & Goto, S., 2009, 2009 International SoC Design Conference, ISOCC 2009. p. 71-74 4 p. 5423878

研究成果: Conference contribution

5 引用 (Scopus)

A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

Liu, K., Min, Y., Yang, X., Sun, H. & Shinohara, H., 2018 12 14, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 161-164 4 p. 8579315. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

研究成果: Conference contribution

1 引用 (Scopus)

A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Konishi, Y., Dosaka, K., Komatsu, T., Ionue, Y., Kumanoya, M., Tobita, Y., Genjyo, H., Nagatomo, M. & Yoshihara, T., 1990 7, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, p. 230-231, 30

研究成果: Conference contribution

7 引用 (Scopus)

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Konishi, Y., Dosaka, K., Komatsu, T., Inoue, Y., Kumanoya, M., Tobita, Y., Genjyo, H., Nagatomo, M. & Yoshihara, T., 1990 10, : : IEEE Journal of Solid-State Circuits. 25, 5, p. 1112-1117 6 p.

研究成果: Article

6 引用 (Scopus)

A 3-Axis Catch-and-Release Gyroscope with Pantograph Vibration for Low-Power and Fast Start-Up Applications

Yuzawa, A., Gando, R., Masunishi, K., Ogawa, E., Hiraga, H., Tomizawa, Y., Itakura, T. & Ikehashi, T., 2019 6, 2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems and Eurosensors XXXIII, TRANSDUCERS 2019 and EUROSENSORS XXXIII. Institute of Electrical and Electronics Engineers Inc., p. 430-433 4 p. 8808391. (2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems and Eurosensors XXXIII, TRANSDUCERS 2019 and EUROSENSORS XXXIII).

研究成果: Conference contribution

A 3D block printer using toy bricks for various models

Sugimoto, C., Maeda, Y., Maekawa, T. & Maruo, S., 2018 1 12, 2017 13th IEEE Conference on Automation Science and Engineering, CASE 2017. IEEE Computer Society, p. 958-963 6 p. (IEEE International Conference on Automation Science and Engineering; 巻数 2017-August).

研究成果: Conference contribution

1 引用 (Scopus)

A 3-dimensional mathematical model of microbial proliferation that generates the characteristic cumulative relative abundance distributions in gut microbiomes

Takayasu, L., Suda, W., Watanabe, E., Fukuda, S., Takanashi, K., Ohno, H., Takayasu, M., Takayasu, H. & Hattori, M., 2017 8 1, : : PLoS One. 12, 8, e0180863.

研究成果: Article

1 引用 (Scopus)

A 3D sensing model and practical sensor placement based on coverage and cost evaluation

Yang, J., Kamezaki, M., Iwata, H. & Sugano, S., 2015 10 2, 2015 IEEE International Conference on Cyber Technology in Automation, Control and Intelligent Systems, IEEE-CYBER 2015. Institute of Electrical and Electronics Engineers Inc., p. 1-6 6 p. 7287900

研究成果: Conference contribution

2 引用 (Scopus)

A 3-D vision system incorporating solid modeler and geometric reasoning

Dohi, H. & Ishizuka, M., 1990, Proceedings - International Conference on Pattern Recognition. Piscataway, NJ, United States: Publ by IEEE, 巻 1. p. 185-187 3 p.

研究成果: Conference contribution

1 引用 (Scopus)

A 3 Jy radio burst at a high galactic latitude

Niinuma, K., Asuma, K., Kuniyoshi, M., Matsumura, N., Takefuji, K., Kida, S., Takeuchi, A., Nakamura, R., Tanaka, T., Suzuki, S. & Daishido, T., 2007 3 1, : : Astrophysical Journal. 657, 1 II

研究成果: Article

26 引用 (Scopus)

A 3V operation RF MEMS variable capacitor using piezoelectric and electrostatic actuation with lithographical bending control

Ikehashi, T., Ogawa, E., Yamazaki, H. & Ohguro, T., 2007 12 1, TRANSDUCERS and EUROSENSORS '07 - 4th International Conference on Solid-State Sensors, Actuators and Microsystems. p. 149-152 4 p. 4300093. (TRANSDUCERS and EUROSENSORS '07 - 4th International Conference on Solid-State Sensors, Actuators and Microsystems).

研究成果: Conference contribution

1 引用 (Scopus)
38 引用 (Scopus)

A 40 dB peak gain, wideband, low noise intermediate frequency (IF) amplifier

Dong, R., Hara, S., Katayama, K., Takano, K., Watanabe, I., Sekine, N., Kasamatsu, A., Yoshida, T., Amakawa, S. & Fujishima, M., 2018 1 8, 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 巻 Part F134147. p. 622-625 4 p.

研究成果: Conference contribution

A 40 degree grid model for multiple 3D objects

Yaku, T., Anzai, K., Miyadera, Y., Anada, K., Goto, T. & Yokota, K., 2016 5 19, Proceedings - 2016 IEEE International Conference on Industrial Technology, ICIT 2016. Institute of Electrical and Electronics Engineers Inc., 巻 2016-May. p. 1678-1683 6 p. 7475015

研究成果: Conference contribution

A 40-Gbit/s 16-bit photonic parallel-to-serial converter

Takenouchi, H., Takahata, K., Nakahara, T., Takahashi, R. & Suzuki, H., 2002 12 1, : : Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS. 1, p. 45-46 2 p.

研究成果: Conference article

6 引用 (Scopus)

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure

Yoshimoto, S., Miyano, S., Takamiya, M., Shinohara, H., Kawaguchi, H. & Yoshimoto, M., 2013 11 7, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 6658537. (Proceedings of the Custom Integrated Circuits Conference).

研究成果: Conference contribution

2 引用 (Scopus)

A 416-mW 32-Gbit/s 300-GHz CMOS receiver

Hara, S., Katayama, K., Takano, K., Dong, R., Watanabe, I., Sekine, N., Kasamatsu, A., Yoshida, T., Amakawa, S. & Fujishima, M., 2017 9 20, 2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017. Institute of Electrical and Electronics Engineers Inc., p. 65-67 3 p. 8048291

研究成果: Conference contribution

4 引用 (Scopus)

A 41mW VGA@30fps quadtree video encoder for video surveillance systems

Liu, Q., Hiratsuka, S., Goto, S. & Ikenaga, T., 2007 12 1, ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. p. 758-761 4 p. 4415741. (ASICON 2007 - 2007 7th International Conference on ASIC Proceeding).

研究成果: Conference contribution

A 41 mW VGA@30 fps quadtree video encoder for video surveillance systems

Liu, Q., Hiratsuka, S., Shimizu, K., Ushiki, S., Goto, S. & Ikenaga, T., 2008 4, : : IEICE Transactions on Electronics. E91-C, 4, p. 449-456 8 p.

研究成果: Article

1 引用 (Scopus)

A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

Yoshida, Y., Kamei, T., Hayase, K., Shibahara, S., Nishii, O., Hattori, T., Hasegawa, A., Takada, M., Irie, N., Uchiyama, K., Odaka, T., Takada, K., Kimura, K. & Kasahara, H., 2007 9 27, 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. p. 100-101+590+95 4242284. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

研究成果: Conference contribution

24 引用 (Scopus)

A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC

Zhou, D., He, G., Fei, W., Chen, Z., Zhou, J. & Goto, S., 2012, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. p. 154-155 2 p. 6243836

研究成果: Conference contribution

7 引用 (Scopus)

A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Nakase, Y. & Shinohara, H., 2009 11 18, 2009 Symposium on VLSI Circuits. p. 158-159 2 p. 5205389. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

59 引用 (Scopus)

A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H. & Akamatsu, H., 2008 1 1, : : IEEE Journal of Solid-State Circuits. 43, 4, p. 938-943 6 p.

研究成果: Article

27 引用 (Scopus)

A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H. & Akamatsu, H., 2007 12 1, 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 254-255 2 p. 4342740. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

12 引用 (Scopus)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC

Yuyama, Y., Ito, M., Kiyoshige, Y., Nitta, Y., Matsui, S., Nishii, O., Hasegawa, A., Ishikawa, M., Yamada, T., Miyakoshi, J., Terada, K., Nojiri, T., Satoh, M., Mizuno, H., Uchiyama, K., Wada, Y., Kimura, K., Kasahara, H. & Maejima, H., 2010 5 18, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. p. 100-101 2 p. 5434031. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 巻数 53).

研究成果: Conference contribution

29 引用 (Scopus)

A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core

Nishii, O., Yuyama, Y., Ito, M., Kiyoshige, Y., Nitta, Y., Ishikawa, M., Yamada, T., Miyakoshi, J., Wada, Y., Kimura, K., Kasahara, H. & Maejima, H., 2011 4, : : IEICE Transactions on Electronics. E94-C, 4, p. 663-669 7 p.

研究成果: Article

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., Yamagami, Y., Ishikura, S., Terano, T., Oashi, T., Hashimoto, K., Sebe, A., Okazaki, G., Satomi, K., Akamatsu, H. & Shinohara, H., 2008, : : IEEE Journal of Solid-State Circuits. 43, 1, p. 180-191 12 p.

研究成果: Article

47 引用 (Scopus)

A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations

Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., Yamagami, Y., Ishikura, S., Terano, T., Oashi, T., Hashimoto, K., Sebe, A., Okazaki, G., Satomi, K., Akamatsu, H. & Shinohara, H., 2007 9 27, 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. p. 326-327+606+321 4242397. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

研究成果: Conference contribution

49 引用 (Scopus)

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oda, Y., Usui, K., Kawamura, T., Tsuboi, N., Iwasaki, T., Hashimoto, K., Makino, H. & Shinohara, H., 2008 9 23, 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC. p. 202-203 2 p. 4586011. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

77 引用 (Scopus)

A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line

Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., Akasaka, Y. & Kayano, S., 1985, : : IEEE Journal of Solid-State Circuits. 20, 5, p. 929-934 6 p.

研究成果: Article

2 引用 (Scopus)

A 45-ns 64-Mb DRAM with a merged match-line test architecture

Mori, S., Miyamoto, H., Morooka, Y., Kikuda, S., Suwa, M., Kinoshita, M., Hachisuka, A., Arima, H., Yamada, M., Yoshihara, T. & Kayano, S., 1991 11, : : IEEE Journal of Solid-State Circuits. 26, 11, p. 1486-1492 7 p.

研究成果: Article

9 引用 (Scopus)
14 引用 (Scopus)

A 4-GHz band ultra-wideband voltage controlled oscillator IC using 0.35 μm SiGe BiCMOS technology

Kurachi, S., Murata, Y., Ishikawa, S., Itoh, N., Yonemura, K. & Yoshimasu, T., 2007 12 1, Proceedings of the 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting. p. 9-12 4 p. 4351827. (Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting).

研究成果: Conference contribution

2 引用 (Scopus)

A 4-phase cross-coupled charge pump with charge sharing clock scheme

Zhu, H., Huang, M., Zhang, Y. & Yoshihara, T., 2011, International Conference on Electronic Devices, Systems, and Applications. p. 73-76 4 p. 5959067

研究成果: Conference contribution

8 引用 (Scopus)
3 引用 (Scopus)

A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

Zhou, D., Zhou, J., He, X., Kong, J., Zhu, J., Liu, P. & Goto, S., 2010, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. p. 171-172 2 p. 5560311

研究成果: Conference contribution

14 引用 (Scopus)

A 530 Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

Zhou, D., Zhou, J., He, X., Zhu, J., Kong, J., Liu, P. & Goto, S., 2011 4, : : IEEE Journal of Solid-State Circuits. 46, 4, p. 777-788 12 p., 5727920.

研究成果: Article

45 引用 (Scopus)

A 530 Mpixels/s intra prediction architecture for ultra high definition H.264/AVC encoder

He, G., Zhou, D., Zhou, J., Zhang, T. & Goto, S., 2011 4, : : IEICE Transactions on Electronics. E94-C, 4, p. 419-427 9 p.

研究成果: Article

1 引用 (Scopus)

A 5-GHz band WLAN SiGe HBT power amplifier IC with novel adaptive-linearizing CMOS bias circuit

Yang, X., Sugiura, T., Otani, N., Murakami, T., Otobe, E. & Yoshimasu, T., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 651-658 8 p.

研究成果: Article

1 引用 (Scopus)