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• A 7-round parallel hardware-saving accelerator for Gaussian and DoG pyramid construction part of SIFT

  Qiu, J., Huang, T. & Ikenaga, T., 2010 12月 29, Computer Vision, ACCV 2009 - 9th Asian Conference on Computer Vision, Revised Selected Papers. PART 3 ed. p. 75-84 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 5996 LNCS, no. PART 3).

  研究成果: Conference contribution
  7 被引用数 (Scopus)

• A 7-Die 3D Stacked 3840 × 2160@120 fps motion estimation processor

  Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2017 3月, In: IEICE Transactions on Electronics. E100C, 3, p. 223-231 9 p.

  研究成果: Article › 査読

• A 75MHz MRAM with pipe-lined self-reference read scheme for mobile/robotics memory system

  Kim, T. Y., Kimura, F., Matsui, Y., Yoshihara, T., Ooishi, T., Kihara, Y. & Hatanaka, M., 2006, 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. p. 117-120 4 p. 4017545

  研究成果: Conference contribution
  4 被引用数 (Scopus)

• A 70-mm-long periodically-poled Mg doped stoichiometric LiNbO₃ for low-threshold optical parametric generation

  Maruyama, M., Hodoyama, K., Nakajima, H., Kurimura, S., Yu, N. E. & Kitamura, K., 2005, Optics InfoBase Conference Papers. Optical Society of America

  研究成果: Conference contribution

• A 70-mm-long periodically-poled Mg doped stoichiometric LiNbO₃ for low-threshold optical parametric generation

  Maruyama, M., Hodoyama, K., Nakajima, H., Kurimura, S., Yu, N. E. & Kitamura, K., 2005, 2005 Conference on Lasers and Electro-Optics, CLEO. Vol. 3. p. 1966-1968 3 p. CThY3

  研究成果: Conference contribution
  2 被引用数 (Scopus)

• A 70-mm-long periodically-poled Mg doped stoichiometric LiNbO₃ for low-threshold optical parametric generation

  Maruyama, M., Hodoyama, K., Nakajima, H., Kurimura, S., Yu, N. E. & Kitamura, K., 2006, Optics InfoBase Conference Papers. Optical Society of America

  研究成果: Conference contribution

• A 6-year cohort study on relationship between functional fitness and impairment of ADL in community-dwelling older persons

  Nagamatsu, T., Oida, Y., Kitabatake, Y., Kohno, H., Egawa, K., Nezu, N. & Arao, T., 2003, In: Journal of Epidemiology. 13, 3, p. 142-148 7 p.

  研究成果: Article › 査読
  12 被引用数 (Scopus)

• A 66-dBc fundamental suppression frequency doubler IC for UWB sensor applications

  Sun, J., Liu, Q., Suh, Y. J., Shibata, T. & Yoshimasu, T., 2011 4月, In: IEICE Transactions on Electronics. E94-C, 4, p. 575-581 7 p.

  研究成果: Article › 査読
  2 被引用数 (Scopus)

• A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

  Hamamoto, T., Furutani, K., Kubo, T., Kawasaki, S., Iga, H., Kono, T., Konishi, Y. & Yoshihara, T., 2004 1月, In: IEEE Journal of Solid-State Circuits. 39, 1, p. 194-206 13 p.

  研究成果: Article › 査読
  31 被引用数 (Scopus)

• A 65 nm ultra-high-density dual-port SRAM with 0.71um² 8T-cell for SoC

  Nii, K., Masuda, Y., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Igarashi, M., Tomita, K., Tsuboi, N., Makino, H., Ishibashi, K. & Shinohara, H., 2006 12月 1, 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 130-131 2 p. 1705344. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

  研究成果: Conference contribution
  19 被引用数 (Scopus)

• A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

  Ohbayashi, S., Yabuuchi, M., Nii, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Igarashi, M., Takeuchi, M., Kawashima, H., Makino, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Ishibashi, K. & Shinohara, H., 2006, 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 17-18 2 p. 1705290. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

  研究成果: Conference contribution
  43 被引用数 (Scopus)

• A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

  Ohbayashi, S., Yabuuchi, M., Nil, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Yoshihara, T., Igarashi, M., Takeuchi, M., Kawashima, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Makino, H., Ishibashi, K. & Shinohara, H., 2007 4月, In: IEEE Journal of Solid-State Circuits. 42, 4, p. 820-829 10 p.

  研究成果: Article › 査読
  99 被引用数 (Scopus)

• A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

  Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., Yonezu, T., Iwamoto, T., Nii, K., Tsukamoto, Y., Arakawa, M., Uchida, T., Qkada, M., Ishii, A., Makino, H., Ishibashi, K. & Shinohara, H., 2007 9月 27, 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. p. 488-489+617+485 4242478. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

  研究成果: Conference contribution
  4 被引用数 (Scopus)

• A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

  Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., Yonezu, T., Iwamoto, T., Nii, K., Tsukamoto, Y., Arakawa, M., Uchida, T., Okada, M., Ishii, A., Yoshihara, T., Makino, H., Ishibashi, K. & Shinohara, H., 2008 1月, In: IEEE Journal of Solid-State Circuits. 43, 1, p. 96-108 13 p.

  研究成果: Article › 査読
  11 被引用数 (Scopus)

• A 64 kb/s Video Coding System and Its Performance

  Hashimoto, H., Watanabe, H. & Suzuki, Y., 1988 10月 25, In: Proceedings of SPIE - The International Society for Optical Engineering. 1001, p. 847-853 7 p.

  研究成果: Conference article › 査読
  9 被引用数 (Scopus)

• A 64-degree grid graph model of the time-continuous 4D objects

  Yaku, T., Anzai, K., Yokota, K., Anada, K. & Miyadera, Y., 2015 11月 23, Proceedings - 3rd International Conference on Applied Computing and Information Technology and 2nd International Conference on Computational Science and Intelligence, ACIT-CSI 2015. Institute of Electrical and Electronics Engineers Inc., p. 129-131 3 p. 7336049

  研究成果: Conference contribution

• A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications

  Zhou, J., Zhou, D., He, X. & Goto, S., 2009, ISPACS 2009 - 2009 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings. p. 49-52 4 p. 5383903

  研究成果: Conference contribution
  1 被引用数 (Scopus)

• A 64-bit carry look ahead adder using pass transistor BiCMOS gates

  Ueda, K., Suzuki, H., Suda, K., Shinohara, H. & Mashiko, K., 1996 6月, In: IEEE Journal of Solid-State Circuits. 31, 6, p. 810-817 8 p.

  研究成果: Article › 査読
  10 被引用数 (Scopus)

• A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications

  Zhao, Y., Zhou, J., Zhou, D. & Goto, S., 2014 1月 28, 2014 IEEE International Conference on Image Processing, ICIP 2014. Institute of Electrical and Electronics Engineers Inc., p. 1268-1272 5 p. 7025253

  研究成果: Conference contribution
  4 被引用数 (Scopus)

• A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function

  Ohsawa, T., Furuyama, T., Watanabe, Y., Tanaka, H., Natori, K., Shinozaki, S., Tanaka, T., Yamano, S., Nagahama, Y., Kushiyama, N. & Tsuchida, K., 1987 10月, In: IEEE Journal of Solid-State Circuits. 22, 5, p. 663-668 6 p.

  研究成果: Article › 査読
  16 被引用数 (Scopus)

• A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

  Nakayama, T., Kobayashi, S. I., Miyawaki, Y., Terada, Y., Ajika, N., Ohi, M., Arima, H., Matsukawa, T., Yoshihara, T. & Suzuki, K., 1991 11月, In: IEEE Journal of Solid-State Circuits. 26, 11, p. 1600-1605 6 p.

  研究成果: Article › 査読
  2 被引用数 (Scopus)

• A 60-GHz point-to-multipoint millimeter-wave fiber-radio communication system

  Choi, S. T., Yang, K. S., Nishi, S., Shimizu, S., Tokuda, K. & Kim, Y. H., 2006 5月, In: IEEE Transactions on Microwave Theory and Techniques. 54, 5, p. 1953-1960 8 p.

  研究成果: Article › 査読
  37 被引用数 (Scopus)

• A 60-GHz compact mobile terminal for full-duplex radio-on-fiber system

  Yang, K. S., Choi, S. T., Kim, Y. H., Nishi, S., Shimizu, S. & Tokuda, K., 2005 3月 20, In: Microwave and Optical Technology Letters. 44, 6, p. 504-507 4 p.

  研究成果: Article › 査読
  3 被引用数 (Scopus)

• A 600MIPS 120mW 70μA leakage triple-CPU mobile application processor chip

  Torii, S., Suzuki, S., Tomonaga, H., Tokue, T., Sakai, J., Suzuki, N., Murakami, K., Hiraga, T., Shigemoto, K., Tatebe, Y., Ohbuchi, E., Kayama, N., Edahiro, M., Kusano, T. & Nishi, N., 2005, In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 48, p. 136-137+589

  研究成果: Conference article › 査読
  36 被引用数 (Scopus)

• A 600MIPS 120mW 70μA leakage triple-CPU mobile application processor chip

  Torii, S., Suzuki, S., Tomonaga, H., Tokue, T., Sakai, J., Suzuki, N., Murakami, K., Hiraga, T., Shigemoto, K., Tatebe, Y., Ohbuchi, E., Kayama, N., Edahiro, M., Kusano, T. & Nishi, N., 2005, In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 48, p. 102-103+553 7.5.

  研究成果: Conference article › 査読
  4 被引用数 (Scopus)

• A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching

  Endoh, T., Togashi, S., Iga, F., Yoshida, Y., Ohsawa, T., Koike, H., Fukami, S., Ikeda, S., Kasai, N., Sakimura, N., Hanyu, T. & Ohno, H., 2011 12月 1, 2011 International Electron Devices Meeting, IEDM 2011. p. 4.3.1-4.3.4 6131487. (Technical Digest - International Electron Devices Meeting, IEDM).

  研究成果: Conference contribution
  11 被引用数 (Scopus)

• A 600-MHz 54 × 54-bit multiplier with rectangular-styled Wallace tree

  Itoh, N., Naemura, Y., Makino, H., Nakase, Y., Yoshihara, T. & Horiba, Y., 2001 2月, In: IEEE Journal of Solid-State Circuits. 36, 2, p. 249-257 9 p.

  研究成果: Article › 査読
  49 被引用数 (Scopus)

• A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip

  Chen, Z., Peng, X., Zhao, X., Okamura, L., Zhou, D. & Goto, S., 2011 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2587-2596 10 p.

  研究成果: Article › 査読
  1 被引用数 (Scopus)

• A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip

  Chen, Z., Peng, X., Zhao, X., Xie, Q., Okamura, L., Zhou, D. & Goto, S., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 7-12 6 p. 6131868

  研究成果: Conference contribution
  5 被引用数 (Scopus)

• A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

  Chen, Z., Peng, X., Zhao, X., Okamura, L., Zhou, D. & Goto, S., 2013, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 87-88 2 p. 6509569

  研究成果: Conference contribution
  1 被引用数 (Scopus)

• A 5-GHz band WLAN SiGe HBT power amplifier IC with novel adaptive-linearizing CMOS bias circuit

  Yang, X., Sugiura, T., Otani, N., Murakami, T., Otobe, E. & Yoshimasu, T., 2015 7月 1, In: IEICE Transactions on Electronics. E98C, 7, p. 651-658 8 p.

  研究成果: Article › 査読
  2 被引用数 (Scopus)

• A 530 Mpixels/s intra prediction architecture for ultra high definition H.264/AVC encoder

  He, G., Zhou, D., Zhou, J., Zhang, T. & Goto, S., 2011 4月, In: IEICE Transactions on Electronics. E94-C, 4, p. 419-427 9 p.

  研究成果: Article › 査読
  1 被引用数 (Scopus)

• A 530 Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

  Zhou, D., Zhou, J., He, X., Zhu, J., Kong, J., Liu, P. & Goto, S., 2011 4月, In: IEEE Journal of Solid-State Circuits. 46, 4, p. 777-788 12 p., 5727920.

  研究成果: Article › 査読
  51 被引用数 (Scopus)

• A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

  Zhou, D., Zhou, J., He, X., Kong, J., Zhu, J., Liu, P. & Goto, S., 2010, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. p. 171-172 2 p. 5560311

  研究成果: Conference contribution
  16 被引用数 (Scopus)

• A 5.83 pj/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65 nm CMOS

  Zhao, X., Chen, Z., Peng, X., Zhou, D. & Goto, S., 2013, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2623-2632 10 p.

  研究成果: Article › 査読

• A 5.5-GHZ sige HBT Doherty amplifier using diode linearizer and lumped-element hybrid coupler

  Liu, H. & Yoshimasu, T., 2008 6月 1, In: Microwave and Optical Technology Letters. 50, 6, p. 1554-1558 5 p.

  研究成果: Article › 査読
  3 被引用数 (Scopus)

• A 4-phase cross-coupled charge pump with charge sharing clock scheme

  Zhu, H., Huang, M., Zhang, Y. & Yoshihara, T., 2011, International Conference on Electronic Devices, Systems, and Applications. p. 73-76 4 p. 5959067

  研究成果: Conference contribution
  10 被引用数 (Scopus)

• A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications

  Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., Zhou, J., Zhang, S., Kimura, S., Yoshimura, T. & Goto, S., 2016 2月 23, 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016. Institute of Electrical and Electronics Engineers Inc., p. 266-268 3 p. 7418009. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 59).

  研究成果: Conference contribution
  22 被引用数 (Scopus)

• A 4-GHz band ultra-wideband voltage controlled oscillator IC using 0.35 μm SiGe BiCMOS technology

  Kurachi, S., Murata, Y., Ishikawa, S., Itoh, N., Yonemura, K. & Yoshimasu, T., 2007 12月 1, Proceedings of the 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting. p. 9-12 4 p. 4351827. (Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting).

  研究成果: Conference contribution
  4 被引用数 (Scopus)

• A 48 cycles/MB H.264/AVC deblocking filter architecture for ultra high definition applications

  Zhou, D., Zhou, J., Zhu, J. & Goto, S., 2009 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3203-3210 8 p.

  研究成果: Article › 査読
  15 被引用数 (Scopus)

• A 45-ns 64-Mb DRAM with a merged match-line test architecture

  Mori, S., Miyamoto, H., Morooka, Y., Kikuda, S., Suwa, M., Kinoshita, M., Hachisuka, A., Arima, H., Yamada, M., Yoshihara, T. & Kayano, S., 1991 11月, In: IEEE Journal of Solid-State Circuits. 26, 11, p. 1486-1492 7 p.

  研究成果: Article › 査読
  9 被引用数 (Scopus)

• A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line

  Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., Akasaka, Y. & Kayano, S., 1985 10月, In: IEEE Journal of Solid-State Circuits. 20, 5, p. 929-934 6 p.

  研究成果: Article › 査読
  2 被引用数 (Scopus)

• A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

  Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oda, Y., Usui, K., Kawamura, T., Tsuboi, N., Iwasaki, T., Hashimoto, K., Makino, H. & Shinohara, H., 2008, 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC. Institute of Electrical and Electronics Engineers Inc., p. 212-213 2 p. 4586011. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

  研究成果: Conference contribution
  94 被引用数 (Scopus)

• A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations

  Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., Yamagami, Y., Ishikura, S., Terano, T., Oashi, T., Hashimoto, K., Sebe, A., Okazaki, G., Satomi, K., Akamatsu, H. & Shinohara, H., 2007 9月 27, 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. p. 326-327+606+321 4242397. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

  研究成果: Conference contribution
  50 被引用数 (Scopus)

• A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

  Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., Yamagami, Y., Ishikura, S., Terano, T., Oashi, T., Hashimoto, K., Sebe, A., Okazaki, G., Satomi, K., Akamatsu, H. & Shinohara, H., 2008 1月, In: IEEE Journal of Solid-State Circuits. 43, 1, p. 180-191 12 p.

  研究成果: Article › 査読
  50 被引用数 (Scopus)

• A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core

  Nishii, O., Yuyama, Y., Ito, M., Kiyoshige, Y., Nitta, Y., Ishikawa, M., Yamada, T., Miyakoshi, J., Wada, Y., Kimura, K., Kasahara, H. & Maejima, H., 2011 4月, In: IEICE Transactions on Electronics. E94-C, 4, p. 663-669 7 p.

  研究成果: Article › 査読

• A 45nm 37.3GOPS/W heterogeneous multi-core SoC

  Yuyama, Y., Ito, M., Kiyoshige, Y., Nitta, Y., Matsui, S., Nishii, O., Hasegawa, A., Ishikawa, M., Yamada, T., Miyakoshi, J., Terada, K., Nojiri, T., Satoh, M., Mizuno, H., Uchiyama, K., Wada, Y., Kimura, K., Kasahara, H. & Maejima, H., 2010 5月 18, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. p. 100-101 2 p. 5434031. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 53).

  研究成果: Conference contribution
  33 被引用数 (Scopus)

• A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

  Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H. & Akamatsu, H., 2007 12月 1, 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 254-255 2 p. 4342740. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

  研究成果: Conference contribution
  12 被引用数 (Scopus)

• A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

  Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H. & Akamatsu, H., 2008 1月, In: IEEE Journal of Solid-State Circuits. 43, 4, p. 938-943 6 p.

  研究成果: Article › 査読
  30 被引用数 (Scopus)

• A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

  Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Nakase, Y. & Shinohara, H., 2009 11月 18, 2009 Symposium on VLSI Circuits. p. 158-159 2 p. 5205389. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

  研究成果: Conference contribution
  68 被引用数 (Scopus)