This article introduces an SRAM-based physically unclonable function (PUF) that employs hybrid-mode operations in the enhancement-enhancement (EE) SRAM mode and CMOS SRAM mode to achieve both high native stability and low power. A data latching scheme based on the hybrid structure enables operations under low supply voltage (V_DD). Furthermore, the proposed hybrid SRAM PUF is compatible with hot carrier injection (HCI) burn-in stabilization, which can reinforce PUF stability to 100% without the requirements of bitcell redundancy, visible oxide damages, additional fabrication processes, helper data storage, or error-correcting code (ECC) circuits. The proposed PUF is fabricated in 130-nm standard CMOS, and the experimental results show that it achieves 0.29% native bit error rate (BER) at the nominal condition of 0.6 V/25 °C. The operating V_DD scales down to 0.5 V, with a core energy efficiency of 2.07 fJ/b. After HCI burn-in, no bit errors are found across all V_DD /temperature (VT) corners from 0.5 to 0.7 V and from -40 °C to 120 °C (5120 bits \times 500 evaluations tested at each condition). Long-term reliability is verified by using an accelerated aging test equivalent to approximately 21 years of operation, where the reinforced PUF shows no bit errors even at the worst VT corner of 0.5 V/120 °C during the test. The introduced hybrid SRAM PUF also passes all applicable NIST SP 800-22 randomness tests. It has a compact bitcell with an area of 497 F2.
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