A 1-Mb STT-MRAM with zero-array standby power and 1.5-ns quick wake-up by 8-b fine-grained power gating

Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

The power gating is one of the key technologies that reduce the operation power of STT-RAMs for enjoying their non-volatility. Especially, the number of memory cells whose supply voltages are simultaneously controlled in the power gating (grain size) is required to be as small as the bit-width in read and write for minimizing the operation power. For this ultra-fine-grained power gating scheme, we proposed a small power line (PL) driver that utilizes an NFET bootstrap circuit. It is found that the size of the macro using this PL driver is almost independent of the grain size with its write and read performance kept constant. Therefore, this PL driver combined with a small grain is shown to realize a nonvolatile embedded memory macro of fast read/write cycles, ultra-low operation power and zero array standby power with no leak path in the PL drivers.

本文言語English
ホスト出版物のタイトル2013 5th IEEE International Memory Workshop, IMW 2013
ページ80-83
ページ数4
DOI
出版ステータスPublished - 2013 9 16
外部発表はい
イベント2013 5th IEEE International Memory Workshop, IMW 2013 - Monterey, CA, United States
継続期間: 2013 5 262013 5 29

出版物シリーズ

名前2013 5th IEEE International Memory Workshop, IMW 2013

Other

Other2013 5th IEEE International Memory Workshop, IMW 2013
国/地域United States
CityMonterey, CA
Period13/5/2613/5/29

ASJC Scopus subject areas

  • ソフトウェア

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