A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma

研究成果: Article査読

6 被引用数 (Scopus)

抄録

A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced "FD-PD mode switching" transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current.

本文言語English
ページ(範囲)1712-1718
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
32
11
DOI
出版ステータスPublished - 1997 11
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「A 1-V 46-ns 16-Mb SOI-DRAM with body control technique」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル