A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

Katsumi Dosaka, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara

研究成果: Article査読

10 被引用数 (Scopus)

抄録

A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm2 is only a 7% increase over the conventional 4-MB DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity.

本文言語English
ページ(範囲)1534-1539
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
27
11
DOI
出版ステータスPublished - 1992 11
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント 「A 100-MHz 4-Mb cache DRAM with fast copy-back scheme」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル