A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

Dajiang Zhou*, Zongyuan You, Jiayi Zhu, Ji Kong, Yu Hong, Xianmin Chen, Xuewen He, Chen Xu, Hang Zhang, Jinjia Zhou, Ning Deng, Peilin Liu, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

20 被引用数 (Scopus)

抄録

In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.

本文言語English
ホスト出版物のタイトルIEEE Symposium on VLSI Circuits, Digest of Technical Papers
ページ262-263
ページ数2
出版ステータスPublished - 2009
外部発表はい
イベント2009 Symposium on VLSI Circuits - Kyoto, Japan
継続期間: 2009 6 162009 6 18

Other

Other2009 Symposium on VLSI Circuits
国/地域Japan
CityKyoto
Period09/6/1609/6/18

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 電子材料、光学材料、および磁性材料

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