A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology

Naoko Ono, Mizuki Motoyoshi, Kyoya Takano, Kosuke Katayama, Ryuichi Fujimoto, Minoru Fujishima

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10-8. The transmitter has an output power of -0.05 dBm.

本文言語English
ホスト出版物のタイトル2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
ページ439-441
ページ数3
DOI
出版ステータスPublished - 2012 12 1
外部発表はい
イベント2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, Taiwan, Province of China
継続期間: 2012 12 42012 12 7

出版物シリーズ

名前Asia-Pacific Microwave Conference Proceedings, APMC

Other

Other2012 Asia-Pacific Microwave Conference, APMC 2012
国/地域Taiwan, Province of China
CityKaohsiung
Period12/12/412/12/7

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル