Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm 2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.
|ホスト出版物のタイトル||2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011|
|出版ステータス||Published - 2011|
|イベント||7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju|
継続期間: 2011 11 14 → 2011 11 16
|Other||7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011|
|Period||11/11/14 → 11/11/16|
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