A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Xiao Peng*, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto

*この研究の対応する著者

    研究成果: Conference contribution

    21 被引用数 (Scopus)

    抄録

    Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm 2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.

    本文言語English
    ホスト出版物のタイトル2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
    ページ317-320
    ページ数4
    DOI
    出版ステータスPublished - 2011
    イベント7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju
    継続期間: 2011 11 142011 11 16

    Other

    Other7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011
    CityJeju
    Period11/11/1411/11/16

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

    フィンガープリント

    「A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル