A 12-bit 3.7-msample/s pipelined A/D converter based on the novel capacitor mismatch calibration technique

Shuaiqi Wang, Fule Li, Yasuaki Inoue

    研究成果: Article

    1 引用 (Scopus)

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    This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 μm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

    元の言語English
    ページ(範囲)2465-2474
    ページ数10
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E91-A
    発行部数9
    DOI
    出版物ステータスPublished - 2008 9

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

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