A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Tohru Furuyama, Yousei Nagahama

研究成果: Article査読

2 被引用数 (Scopus)

抄録

A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

本文言語English
ページ(範囲)479-483
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
26
4
DOI
出版ステータスPublished - 1991 4
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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