A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Tohru Furuyama, Yousei Nagahama

研究成果: Article

2 引用 (Scopus)

抜粋

A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

元の言語English
ページ(範囲)479-483
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
26
発行部数4
DOI
出版物ステータスPublished - 1991 4
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Kushiyama, N., Watanabe, Y., Ohsawa, T., Muraoka, K., Furuyama, T., & Nagahama, Y. (1991). A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation. IEEE Journal of Solid-State Circuits, 26(4), 479-483. https://doi.org/10.1109/4.75042