A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications

Hajime Kubosawa*, Hiromasa Takahashi, Satoshi Ando, Yoshimi Asada, Akira Asato, Atsuhiro Suga, Michihide Kimura, Naoshi Higaki, Hideo Miyake, Tomio Sato, Hideaki Anbutsu, Toshitaka Tsuda, Tetsuo Yoshimura, Isao Amano, Mutsuaki Kai, Shin Mitarai



    3 被引用数 (Scopus)


    We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including a) MPEG2 (MP@Ml.) decoding and graphic processing capabilities for three-dimensional images, b) programming flexibility. and c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84 × 10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V.

    ジャーナルIEEE Journal of Solid-State Circuits
    出版ステータスPublished - 1998 11

    ASJC Scopus subject areas

    • 電子工学および電気工学


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