A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput

Hiroshi Nakamura, Kenichi Imamiya, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian Chen

研究成果: Conference article

2 引用 (Scopus)

抜粋

A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.

元の言語English
ページ(範囲)82-83+411
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
発行部数SUPPL.
出版物ステータスPublished - 2002 1 1
イベント2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
継続期間: 2002 2 32002 2 7

    フィンガープリント

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Nakamura, H., Imamiya, K., Himeno, T., Yamamura, T., Ikehashi, T., Takeuchi, K., Kanda, K., Hosono, K., Futatsuyama, T., Kawai, K., Shirota, R., Arai, N., Arai, F., Hatakeyama, K., Hazama, H., Saito, M., Meguro, H., Conley, K., Quader, K., & Chen, J. (2002). A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, (SUPPL.), 82-83+411.