A 125 mm2 1 Gb NAND flash memory with 10 MB/s program throughput

Hiroshi Nakamura, Kenichi Imamiya, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian Chen

研究成果: Conference article

8 引用 (Scopus)

抜粋

A 125 mm2 1 Gb NAND flash memory with 10 MB/s program throughput was presented. The 1 Gb flash has the highest memory density among 2LC memories and the highest cell/chip efficiency among flash memories. Two techniques were adopted in the architecture for reducing the chip size, the number of memory cells in a NAND string was changed to 32 and each word line (WL) crossed (1024+32)×16 bit lines.

元の言語English
ページ(範囲)106-107+450+99
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
出版物ステータスPublished - 2002 1 1
外部発表Yes
イベント2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
継続期間: 2002 2 32002 2 7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • これを引用

    Nakamura, H., Imamiya, K., Himeno, T., Yamamura, T., Ikehashi, T., Takeuchi, K., Kanda, K., Hosono, K., Futatsuyama, T., Kawai, K., Shirota, R., Arai, N., Arai, F., Hatakeyama, K., Hazama, H., Saito, M., Meguro, H., Conley, K., Quader, K., & Chen, J. (2002). A 125 mm2 1 Gb NAND flash memory with 10 MB/s program throughput. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 106-107+450+99.