A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-μm CMOS STI technology. The effective cell size including the select transistors is 0.077 μm2. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm2 and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The higest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.
ASJC Scopus subject areas
- Electrical and Electronic Engineering