A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed

Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Chen

研究成果: Article

22 引用 (Scopus)

抜粋

A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-μm CMOS STI technology. The effective cell size including the select transistors is 0.077 μm2. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm2 and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The higest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.

元の言語English
ページ(範囲)1493-1501
ページ数9
ジャーナルIEEE Journal of Solid-State Circuits
37
発行部数11
DOI
出版物ステータスPublished - 2002 11 1
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Imamiya, K., Nakamura, H., Himeno, T., Yamamura, T., Ikehashi, T., Takeuchi, K., Kanda, K., Hosono, K., Futatsuyama, T., Kawai, K., Shirota, R., Arai, N., Arai, F., Hatakeyama, K., Hazama, H., Saito, M., Meguro, H., Conley, K., Quader, K., & Chen, J. J. (2002). A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed. IEEE Journal of Solid-State Circuits, 37(11), 1493-1501. https://doi.org/10.1109/JSSC.2002.802355