A 1.41 W H.264/AVC real-time encoder soc for HDTV1080P

Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Ngfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga

研究成果: Conference contribution

40 被引用数 (Scopus)

抄録

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5Gbps 64Mb System-in-Silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.1.8μm CMOS technology, the SoC core occupies 27.1 mm2 die area and consumes 1.41W at 200MHz in typical work conditions.

本文言語English
ホスト出版物のタイトル2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
ページ12-13
ページ数2
DOI
出版ステータスPublished - 2007 12 1
イベント2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
継続期間: 2007 6 142007 6 16

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2007 Symposium on VLSI Circuits, VLSIC
CountryJapan
CityKyoto
Period07/6/1407/6/16

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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