A 15-bit 10-Msample/s pipelined A/D converter based on incomplete settling principle

Shuaiqi Wang*, Fule Li, Yasuaki Inoue

*この研究の対応する著者

    研究成果査読

    1 被引用数 (Scopus)

    抄録

    This paper proposes a 15-bit 10-MS/s pipelined ADC based on the incomplete settling principle. The traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. The proposed ADC verifies the correction and validity of optimizing ADCs' conversion speed without additional power consumption through the incomplete settling. This ADC employs scaling-down scheme to achieve low power dissipation and utilizes full-differential structure, bottom-plate-sampling, and capacitor-sharing techniques as well as bit-by-bit digital self-calibration to increase the ADC's linearity. It is processed in 0.18 μm 1P6M CMOS mixed-mode technology. Simulation results show that 82 dB SNDR and 87 dB SFDR are obtained at the sampling rate of 10 MHz with the input sine frequency of 100 kHz and the whole static power dissipation is 21.94 mW.

    本文言語English
    ページ(範囲)2732-2739
    ページ数8
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E89-A
    10
    DOI
    出版ステータスPublished - 2006 10

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • ハードウェアとアーキテクチャ
    • 情報システム

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