A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

Shuaiqi Wang*, Fule Li, Yasuaki Inoue

*この研究の対応する著者

    研究成果: Conference contribution

    抄録

    This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

    本文言語English
    ホスト出版物のタイトル2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings
    ページ2176-2180
    ページ数5
    4
    DOI
    出版ステータスPublished - 2006
    イベント2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin
    継続期間: 2006 6 252006 6 28

    Other

    Other2006 International Conference on Communications, Circuits and Systems, ICCCAS
    CityGuilin
    Period06/6/2506/6/28

    ASJC Scopus subject areas

    • 電子工学および電気工学

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