A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

Yimeng Zhang, Leona Okamura, Nan Wang, Tsutomu Yoshihara

    研究成果: Conference contribution

    抜粋

    In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

    元の言語English
    ホスト出版物のタイトル2010 International SoC Design Conference, ISOCC 2010
    ページ127-130
    ページ数4
    DOI
    出版物ステータスPublished - 2010
    イベント2010 International SoC Design Conference, ISOCC 2010 - Incheon
    継続期間: 2010 11 222010 11 23

    Other

    Other2010 International SoC Design Conference, ISOCC 2010
    Incheon
    期間10/11/2210/11/23

    ASJC Scopus subject areas

    • Hardware and Architecture

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  • これを引用

    Zhang, Y., Okamura, L., Wang, N., & Yoshihara, T. (2010). A 160MHz 4-bit pipeline multiplier using charge recovery logic technology. : 2010 International SoC Design Conference, ISOCC 2010 (pp. 127-130). [5682955] https://doi.org/10.1109/SOCDC.2010.5682955