In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.
|ホスト出版物のタイトル||2010 International SoC Design Conference, ISOCC 2010|
|出版ステータス||Published - 2010|
|イベント||2010 International SoC Design Conference, ISOCC 2010 - Incheon|
継続期間: 2010 11 22 → 2010 11 23
|Other||2010 International SoC Design Conference, ISOCC 2010|
|Period||10/11/22 → 10/11/23|
ASJC Scopus subject areas