This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.
|ホスト出版物のタイトル||2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011|
|出版ステータス||Published - 2011|
|イベント||7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju|
継続期間: 2011 11月 14 → 2011 11月 16
|Other||7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011|
|Period||11/11/14 → 11/11/16|
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