TY - JOUR
T1 - A 2.5-Ghz 1-V high efficiency CMOS power amplifier IC with a dual-switching transistor and third harmonic tuning technique
AU - Kurniawan, Taufiq Alif
AU - Yoshimasu, Toshihiko
N1 - Funding Information:
This work is funded by Japan Society for the Promotion of Science (JSPS) KAKENHI Grant-in-Aid for Scientific Research (B) Number 23360162. The publication process received no external funding. Acknowledgments: This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems Inc., Mentor Graphics Inc., and Keysight Technologies Japan Ltd.
Publisher Copyright:
© 2019 by the authors. Licensee MDPI, Basel, Switzerland.
PY - 2019/1/1
Y1 - 2019/1/1
N2 - This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.
AB - This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.
KW - CMOS power amplifier IC
KW - Dual-switching transistor
KW - High efficiency
KW - Low voltage
KW - Third harmonic tuning
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U2 - 10.3390/electronics8010069
DO - 10.3390/electronics8010069
M3 - Article
AN - SCOPUS:85060210395
SN - 2079-9292
VL - 8
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
IS - 1
M1 - 69
ER -