A 2.5-Ghz 1-V high efficiency CMOS power amplifier IC with a dual-switching transistor and third harmonic tuning technique

Taufiq Alif Kurniawan, Toshihiko Yoshimasu

研究成果: Article

抄録

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

元の言語English
記事番号69
ジャーナルElectronics (Switzerland)
8
発行部数1
DOI
出版物ステータスPublished - 2019 1 1

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Power amplifiers
Transistors
Tuning
Electric potential
Drain current
Electric power utilization
Networks (circuits)

Keywords

    ASJC Scopus subject areas

    • Control and Systems Engineering
    • Signal Processing
    • Hardware and Architecture
    • Computer Networks and Communications
    • Electrical and Electronic Engineering

    これを引用

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    title = "A 2.5-Ghz 1-V high efficiency CMOS power amplifier IC with a dual-switching transistor and third harmonic tuning technique",
    abstract = "This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5{\%} and a saturated output power of 10.1 dBm.",
    keywords = "CMOS power amplifier IC, Dual-switching transistor, High efficiency, Low voltage, Third harmonic tuning",
    author = "Kurniawan, {Taufiq Alif} and Toshihiko Yoshimasu",
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    AU - Yoshimasu, Toshihiko

    PY - 2019/1/1

    Y1 - 2019/1/1

    N2 - This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

    AB - This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

    KW - CMOS power amplifier IC

    KW - Dual-switching transistor

    KW - High efficiency

    KW - Low voltage

    KW - Third harmonic tuning

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