A 26-GHz-band high back-off efficiency stacked-FET power amplifier IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI

Toshihiko Yoshimasu*, Mengchu Fang, Tsuyoshi Sugiura

*この研究の対応する著者

研究成果: Article査読

抄録

This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.

本文言語English
ページ(範囲)477-483
ページ数7
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E104A
2
DOI
出版ステータスPublished - 2021 2 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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