A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS

研究成果: Conference contribution

1 引用 (Scopus)

抜粋

This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.

元の言語English
ホスト出版物のタイトルEDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits
出版者Institute of Electrical and Electronics Engineers Inc.
ページ1-2
ページ数2
2017-January
ISBN(電子版)9781538629079
DOI
出版物ステータスPublished - 2017 12 1
イベント13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017 - Hsinchu, Taiwan, Province of China
継続期間: 2017 10 182017 10 20

Other

Other13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017
Taiwan, Province of China
Hsinchu
期間17/10/1817/10/20

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Sato, H., Yanagisawa, M., & Yoshimasu, T. (2017). A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. : EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits (巻 2017-January, pp. 1-2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2017.8126403