A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications

Dajiang Zhou*, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

18 被引用数 (Scopus)

抄録

8Kx4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way to being the next digital TV standard. In addition, advanced 3DTV specifications involving a large number of camera views are targeted by emerging applications such as free-viewpoint TV (FTV). This paper presents a single-chip design that supports real-time H.264 decoding of SHV or up to 32 HD views. The design of the chip involved 3 key challenges: 1) Data dependencies of video coding algorithms restrict the degree of hardware parallelism. For SHV, each macroblock (MB) should be processed in less than 40 cycles at 300MHz, which is difficult to meet with a single pipeline; 2) due to the massive design and verification effort for video decoders, a scalable architecture that allows the maximum reuse of existing IP is desirable; and 3) the DRAM bandwidth requirements are always a bottleneck in high-throughput video decoders.

本文言語English
ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ページ224-225
ページ数2
55
DOI
出版ステータスPublished - 2012
外部発表はい
イベント59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States
継続期間: 2012 2月 192012 2月 23

Other

Other59th International Solid-State Circuits Conference, ISSCC 2012
国/地域United States
CitySan Francisco, CA
Period12/2/1912/2/23

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 電子材料、光学材料、および磁性材料

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