A 333MHz random cycle DRAM using the floating body cell

Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa

研究成果: Conference contribution

10 引用 (Scopus)

抜粋

A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells.

元の言語English
ホスト出版物のタイトルProceedings of the IEEE 2005 Custom Integrated Circuits Conference
出版者Institute of Electrical and Electronics Engineers Inc.
ページ259-262
ページ数4
ISBN(印刷物)0780390237, 9780780390232
DOI
出版物ステータスPublished - 2005
イベントIEEE 2005 Custom Integrated Circuits Conference - San Jose, CA, United States
継続期間: 2005 9 182005 9 21

出版物シリーズ

名前Proceedings of the Custom Integrated Circuits Conference
2005
ISSN(印刷物)0886-5930

Other

OtherIEEE 2005 Custom Integrated Circuits Conference
United States
San Jose, CA
期間05/9/1805/9/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Hatsuda, K., Fujita, K., & Ohsawa, T. (2005). A 333MHz random cycle DRAM using the floating body cell. : Proceedings of the IEEE 2005 Custom Integrated Circuits Conference (pp. 259-262). [1568656] (Proceedings of the Custom Integrated Circuits Conference; 巻数 2005). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2005.1568656