A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon

Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, Shimpei Kayano

研究成果: Article査読

12 被引用数 (Scopus)

抄録

This paper will describe a 128-kbit word × 8-bit CMOS SRAM with an access time of 34 ns and a standby current of 2 µA. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-µm minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transistion detection (ATD) are used. This RAM has a “flash-clear” function in which logical zero's are written into all memory cells in less than 1 μs.

本文言語English
ページ(範囲)727-732
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
22
5
DOI
出版ステータスPublished - 1987 10
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント 「A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル