A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon

Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, Shimpei Kayano

研究成果: Article

12 引用 (Scopus)

抜粋

This paper will describe a 128-kbit word × 8-bit CMOS SRAM with an access time of 34 ns and a standby current of 2 µA. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-µm minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transistion detection (ATD) are used. This RAM has a “flash-clear” function in which logical zero's are written into all memory cells in less than 1 μs.

元の言語English
ページ(範囲)727-732
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
22
発行部数5
DOI
出版物ステータスPublished - 1987 10
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Wada, T., Hirose, T., Shinohara, H., Kawai, Y., Yuzuriha, K., Kohno, Y., & Kayano, S. (1987). A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon. IEEE Journal of Solid-State Circuits, 22(5), 727-732. https://doi.org/10.1109/JSSC.1987.1052806