A 35 ns 16K NMOS Static RAM

Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Yoshihiro Hirata, Hiroshi Harada, Takao Nakano

研究成果: Article

1 被引用数 (Scopus)

抄録

An NMOS 16K × 1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 μm gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.

本文言語English
ページ(範囲)815-820
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
17
5
DOI
出版ステータスPublished - 1982 10
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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