A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

Yu Hong, Peilin Liu, Hang Zhang, Zongyuan You, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    5 引用 (Scopus)

    抜粋

    This paper presents a VLSI architecture of CABAC decoder for H.264/AVC Level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying Context Pre-fetch Register Set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13μm technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.

    元の言語English
    ホスト出版物のタイトル2009 International SoC Design Conference, ISOCC 2009
    ページ71-74
    ページ数4
    DOI
    出版物ステータスPublished - 2009
    イベント2009 International SoC Design Conference, ISOCC 2009 - Busan
    継続期間: 2009 11 222009 11 24

    Other

    Other2009 International SoC Design Conference, ISOCC 2009
    Busan
    期間09/11/2209/11/24

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • これを引用

    Hong, Y., Liu, P., Zhang, H., You, Z., Zhou, D., & Goto, S. (2009). A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications. : 2009 International SoC Design Conference, ISOCC 2009 (pp. 71-74). [5423878] https://doi.org/10.1109/SOCDC.2009.5423878