This paper presents a VLSI architecture of CABAC decoder for H.264/AVC Level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying Context Pre-fetch Register Set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13μm technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.
|ホスト出版物のタイトル||2009 International SoC Design Conference, ISOCC 2009|
|出版ステータス||Published - 2009|
|イベント||2009 International SoC Design Conference, ISOCC 2009 - Busan|
継続期間: 2009 11 22 → 2009 11 24
|Other||2009 International SoC Design Conference, ISOCC 2009|
|Period||09/11/22 → 09/11/24|
ASJC Scopus subject areas