A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Yasuhiro Konishi*, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Ionue, Masaki Kumanoya, Yoichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

*この研究の対応する著者

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44-μA current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.

本文言語English
ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
出版社Publ by IEEE
ページ230-231, 30
出版ステータスPublished - 1990 7
外部発表はい
イベント1990 IEEE International Solid-State Circuits Conference - 37th ISSCC - San Francisco, CA, USA
継続期間: 1990 2 141990 2 16

Other

Other1990 IEEE International Solid-State Circuits Conference - 37th ISSCC
CitySan Francisco, CA, USA
Period90/2/1490/2/16

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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