A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

研究成果: Article

6 引用 (Scopus)

抜粋

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.

元の言語English
ページ(範囲)1112-1117
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
25
発行部数5
DOI
出版物ステータスPublished - 1990 10
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Konishi, Y., Dosaka, K., Komatsu, T., Inoue, Y., Kumanoya, M., Tobita, Y., Genjyo, H., Nagatomo, M., & Yoshihara, T. (1990). A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. IEEE Journal of Solid-State Circuits, 25(5), 1112-1117. https://doi.org/10.1109/4.62131