A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

研究成果: Article査読

6 被引用数 (Scopus)

抄録

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.

本文言語English
ページ(範囲)1112-1117
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
25
5
DOI
出版ステータスPublished - 1990 10
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント 「A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル