A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

Yutaka Yoshida*, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

*この研究の対応する著者

研究成果: Conference contribution

24 被引用数 (Scopus)

抄録

A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.

本文言語English
ホスト出版物のタイトル2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
ページ100-101+590+95
DOI
出版ステータスPublished - 2007 9 27
イベント54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
継続期間: 2007 2 112007 2 15

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN(印刷版)0193-6530

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
国/地域United States
CitySan Francisco, CA
Period07/2/1107/2/15

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

フィンガープリント

「A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル