This paper presents a 25-GHz-band 4-stacked-FET highly linear high efficiency power amplifier IC in 45-nm CMOS SOI. A novel load circuit which is adaptively controlled by a bias circuit is proposed to achieve high back-off efficiency. A 4-stacked-FET is utilized to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The power amplifier IC is designed, fabricated, and fully evaluated on-wafer. At a supply voltage of 4.5 V, the power amplifier IC has exhibited an output power of 21.1 dBm with a PAE as high as 42.5% at the 1-dB gain compression point (P1dB). In addition, a saturated output power of 22.7 dBm and a peak PAE of 44.3% are obtained. The measured PAEs at 3-dB and 6-dB back-off from P1dB are 35.1% and 21.6%, respectively.