A 44.3% Peak PAE 25-GHz Stacked-FET Linear Power Amplifier IC with A Varactor-Based Novel Adaptive Load Circuit in 45 nm CMOS SOI

研究成果: Conference contribution

抄録

This paper presents a 25-GHz-band 4-stacked-FET highly linear high efficiency power amplifier IC in 45-nm CMOS SOI. A novel load circuit which is adaptively controlled by a bias circuit is proposed to achieve high back-off efficiency. A 4-stacked-FET is utilized to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The power amplifier IC is designed, fabricated, and fully evaluated on-wafer. At a supply voltage of 4.5 V, the power amplifier IC has exhibited an output power of 21.1 dBm with a PAE as high as 42.5% at the 1-dB gain compression point (P1dB). In addition, a saturated output power of 22.7 dBm and a peak PAE of 44.3% are obtained. The measured PAEs at 3-dB and 6-dB back-off from P1dB are 35.1% and 21.6%, respectively.

本文言語English
ホスト出版物のタイトル2021 IEEE Asia-Pacific Microwave Conference, APMC 2021
出版社Institute of Electrical and Electronics Engineers Inc.
ページ181-183
ページ数3
ISBN(電子版)9781665437820
DOI
出版ステータスPublished - 2021
イベント2021 IEEE Asia-Pacific Microwave Conference, APMC 2021 - Virtual, Online, Australia
継続期間: 2021 11月 282021 12月 1

出版物シリーズ

名前Asia-Pacific Microwave Conference Proceedings, APMC
2021-November

Conference

Conference2021 IEEE Asia-Pacific Microwave Conference, APMC 2021
国/地域Australia
CityVirtual, Online
Period21/11/2821/12/1

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「A 44.3% Peak PAE 25-GHz Stacked-FET Linear Power Amplifier IC with A Varactor-Based Novel Adaptive Load Circuit in 45 nm CMOS SOI」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル