A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu

研究成果: Article

27 被引用数 (Scopus)

抄録

We propose a new -port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (RAV) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 μm3, This 2-port SRAM macro achieves 7 times faster access time without misreading.

本文言語English
ページ(範囲)938-943
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
43
4
DOI
出版ステータスPublished - 2008 1 1
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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