A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

K. Nii*, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara

*この研究の対応する著者

研究成果: Conference contribution

93 被引用数 (Scopus)

抄録

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

本文言語English
ホスト出版物のタイトル2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
出版社Institute of Electrical and Electronics Engineers Inc.
ページ212-213
ページ数2
ISBN(印刷版)9781424418053
DOI
出版ステータスPublished - 2008
外部発表はい
イベント2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC - Honolulu, HI, United States
継続期間: 2008 6 182008 6 20

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
国/地域United States
CityHonolulu, HI
Period08/6/1808/6/20

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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