A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara

研究成果: Conference contribution

89 引用 (Scopus)

抜粋

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

元の言語English
ホスト出版物のタイトル2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
出版者Institute of Electrical and Electronics Engineers Inc.
ページ212-213
ページ数2
ISBN(印刷物)9781424418053
DOI
出版物ステータスPublished - 2008
イベント2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC - Honolulu, HI, United States
継続期間: 2008 6 182008 6 20

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
United States
Honolulu, HI
期間08/6/1808/6/20

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oda, Y., Usui, K., Kawamura, T., Tsuboi, N., Iwasaki, T., Hashimoto, K., Makino, H., & Shinohara, H. (2008). A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. : 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC (pp. 212-213). [4586011] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2008.4586011