A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line

Hirofumi Shinohara, Kenji Anami, Katsuki Ichinose, Tomohisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, Shinpei Kayano

研究成果: Article

2 引用 (Scopus)


This paper describes a 32K words by 8-bit static RAM fabricated with a CMOS technology. The key feature of the RAM is a tri-level word line, in which an automatic power down by a pulsed word line in the read cycle and a power saving by a middle-level word line in the WRITE cycle are combined. This circuit technique minimizes bit-line swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 13- μm design rule enabled layout of the NMOS memory cell in an area of 116.0 μm2 and the die in 49.6 mm2.

ジャーナルIEEE Journal of Solid-State Circuits
出版物ステータスPublished - 1985

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

フィンガープリント A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., Akasaka, Y., & Kayano, S. (1985). A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line. IEEE Journal of Solid-State Circuits, 20(5), 929-934. https://doi.org/10.1109/JSSC.1985.1052417