A 45-ns 64-Mb DRAM with a merged match-line test architecture

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

研究成果: Article

9 引用 (Scopus)

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A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm2 has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm2, and 30-fF cell capacitance has been achieved using an oxynitride layer (teff = 5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time.

元の言語English
ページ(範囲)1486-1492
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
26
発行部数11
DOI
出版物ステータスPublished - 1991 11
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Mori, S., Miyamoto, H., Morooka, Y., Kikuda, S., Suwa, M., Kinoshita, M., Hachisuka, A., Arima, H., Yamada, M., Yoshihara, T., & Kayano, S. (1991). A 45-ns 64-Mb DRAM with a merged match-line test architecture. IEEE Journal of Solid-State Circuits, 26(11), 1486-1492. https://doi.org/10.1109/4.98962