A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, Y. Nakase, H. Shinohara

研究成果: Conference contribution

63 被引用数 (Scopus)

抄録

We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline (BL) enables us to achieve not only low power and high access speed, but also the large cell stability and write ability. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our proposal and confirmed that the 1Mbit-SRAM successfully operated at 0.6V. The active power is reduced by 66%, compared to the conventional 6T-SRAM.

本文言語English
ホスト出版物のタイトル2009 Symposium on VLSI Circuits
ページ158-159
ページ数2
出版ステータスPublished - 2009 11 18
外部発表はい
イベント2009 Symposium on VLSI Circuits - Kyoto, Japan
継続期間: 2009 6 162009 6 18

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09/6/1609/6/18

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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