A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

S. Ishikura*, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu

*この研究の対応する著者

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BI-×512WL 64Kb 2P-SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process [1].

本文言語English
ホスト出版物のタイトル2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
ページ254-255
ページ数2
DOI
出版ステータスPublished - 2007 12 1
外部発表はい
イベント2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
継続期間: 2007 6 142007 6 16

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2007 Symposium on VLSI Circuits, VLSIC
国/地域Japan
CityKyoto
Period07/6/1407/6/16

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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