A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations

Makoto Yabuuchi*, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

*この研究の対応する著者

研究成果: Conference contribution

50 被引用数 (Scopus)

抄録

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245μm2 and 0.327μm2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

本文言語English
ホスト出版物のタイトル2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
ページ326-327+606+321
DOI
出版ステータスPublished - 2007 9 27
外部発表はい
イベント54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
継続期間: 2007 2 112007 2 15

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN(印刷版)0193-6530

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
国/地域United States
CitySan Francisco, CA
Period07/2/1107/2/15

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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