A 530 Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

Dajiang Zhou*, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto

*この研究の対応する著者

研究成果: Article査読

49 被引用数 (Scopus)

抄録

The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096×2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

本文言語English
論文番号5727920
ページ(範囲)777-788
ページ数12
ジャーナルIEEE Journal of Solid-State Circuits
46
4
DOI
出版ステータスPublished - 2011 4
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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